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CXK77B3610GB -6/7
High Speed Bi-CMOS Synchronous Static RAM
Description The CXK77B3610GB-6/7 is a high speed 1M bit Bi-CMOS synchronous statis RAM organized as 32768 words by 36 bits. This SRAM integrates input registers, high speed SRAM and write buffer onto a single monolithic IC and features the delayed write system to reduce the dead cycles. Features * Fast cycle time (Cycle) (Frequency) CXK77B3610GB-6 6ns 166MHz CXK77B3610GB-7 7ns 142MHz * Inputs and outputs are LVTTL/LVCMOS compatible * Single 3.3V power supply: 3.3V 0.15V * Byte-write possible * OE asynchronization * JTAG test circuit * Package 119TBGA * 3 kinds of synchronous operation mode Register-Register mode (R-R mode) Register-Flow Thru mode (R-F mode) Register-Latch mode (R-L mode) Function 32768 word x 36bit High Speed Bi-CMOS Synchronous SRAM Structure Silicon gate Bi-CMOS IC
Preliminary
For the availability of this product, please contact the sales office.
119 pin BGA (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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PE95128-PS
CXK77B3610GB
Block Diagram
15 A0 to 14
Input Reg.
2:1 Mux
Add. Dout
Write Store Reg.
32K x 36 Din Write pulse
2:1 Mux
Output latch
DQ
Reg.
Read Comp. S Reg.
W
Reg.
Salf Time Write Logic
4 BW a to d Reg.
K/K
Output Clock
M1 M2
Mode Control
G
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CXK77B3610GB
Pin Configuration (Top View) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 A NC A DQc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQd A NC TME 3 A NC A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS M1 A TDI 4 NC NC VDD NC S G NC NC VDD K K W A A VDD A TCK 5 A NC A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS M2 A TDO 6 A NC A DQb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQa A NC NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
Pin Description Symbol A DQx K K W BWx S Description Address Input Data I/O in byte a to d Positive Clock Negative Clock Write Enable Byte Write Enable (a to d) Chip Select Symbol G ZZ TCK TMS TDI TDO VDD Description Asyn Output Enable Sleep Mode Select JTAG Clock JTAG Mode Select JTAG Data In JTAG Data Out +3.3V power supply Symbol VDDQ VSS M1, M2 NC Description Output power supply Ground Mode Select No Connect
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CXK77B3610GB
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Allowable power dissipation operating temperature Strorage temperature Soldering temperature * time Symbol VCC VIN VO PD Topr Tstg Tsolder Rating -0.5 to +4.6
(Ta = 25C, GND = 0V) Unit V V V W C C C * sec
-0.5 to VCC +0.5 (4.6V max.) -0.5 to VCC +0.5 (4.6V max.) TBD 0 to 70 -55 to +150 235 * 10
Truth Table ZZ H L L L L L L S (tn) X H L L L L L W (tn) BWx (tn) X X H H L L L X X X X L X H G X X H L X X X Mode Sleep mode, Power down Deselect Read Read Write all bytes (bits 0 to 35) Write bytes with BWx = L Aborted Write DQ0 to 35 DQ0 to 35 VDD (tn) (tn+1) Current Hi-Z X Hi-Z X X X X Hi-Z Hi-Z Hi-Z Q (tn) D (tn) D (tn) X ISB ICC ICC ICC ICC ICC ICC
DC Recommended Operating Conditions Item Supply voltage Output supply voltage Input high voltage Input low voltage Differential clock input signal Differential clock input common mode Symbol VDD VDDQ VIH VIL VK VK, COM Min. 3.15 3.15 2.0 -0.3 0.4 1.2
(Ta = 25C, GND = 0V) Typ. 3.3 3.3 -- -- 0.8 2.0 Max. 3.45 3.45 VDD +0.3 0.8 -- 2.2 Unit V V V V V V
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CXK77B3610GB
Mode Select Truth Table Item Register-Resister mode Register-Flow Thru mode Register-Latch mode M1 L L H M2 H L L
Electrical Characteristics * DC and operating characteristics Item Input leakage current Output leakage current Operating power supply current Standby current Output high voltage Output low voltage VCC = 3.3V, Ta = 25C Symbol ILI ILO (VCC = 3.3V 10%, GND = 0V, Ta = 0 to 70C) Test conditions VIN = GND to VCC VO = GND to VCC G = VIH Cycle = min. Duty = 100% IOUT = 0mA ZZ VIH IOH = -2.0mA IOL = 2.0mA 2.4 -- -- -- Min. -1 -10 Typ. -- -- Max. 1 10 Unit A A
ICC ISB VOH VOL
--
--
TBD 20 -- 0.4
mA mA V V
* I/O capacitance Item Input capacitance Clock input capacitance Output capacitance Symbol CIN CCLK COUT Test conditions VIN = 0V VIN = 0V VOUT = 0V
(Ta = 25C, f = 1MHz) Min. -- -- -- Max. 5 8 8 Unit pF pF pF
Note) These parameters are sampled and are not 100% tested.
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CXK77B3610GB
* AC Electrical Characteristics Item Address access (except Register-Register mode) Clock period Clock pulse high Clock pulse low Setup time Hold time Clock high to output (R-R mode) Clock high to output (R-F mode, R-L mode) Clock low to output (R-L mode) Write cycle clock high to following Read cycle output (R-F mode, R-L mode) Clock high to output high impedance (S deselect cycle) Write cycle clock high to output high impedance (R-F mode, R-L mode) Clock high to output low impedance (R-R mode) Clock high to output low impedance (R-F mode) Clock low to output low impedance (R-L mode) Output enable to output valid (G) Output enable to output in low Z (G) Output disable to output in high Z (G) Symbol -6 Min. -- 6 2 2 0.5 1 1.52 -- 1.52 Max. 9 -- -- -- -- -- 3 6 3 15 1.5 1.5 1.5 2 1.5 -- 1 -- 3 3 -- -- -- 3 -- 3 1.5 1.5 1.5 2 1.5 -- 1 -- Min. -- 7 3 3 1 1 1.52 -- 1.52 -7 Max. 10 -- -- -- -- -- 3.5 7 3.5 17 3.5 3.5 -- -- -- 3.5 -- 3.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tAA tKP tKH tKL tS tH tKQ tKQ1 tKQ2 tKQ3 tHZ2 tWHZ2 tLZ2 tLZ12 tLZ22 tOE tOLZ2 tOHZ2
1 All parameters are specified over the range 0 to 70C. 2 These parameters are sampled and are not 100% tested.
AC characteristics * AC test conditions Item Input pulse high level Input pulse low level Input rise & fall time Input reference level Clock input reference level Clock input differential signal Clock input rise & fall time Output reference level Output load conditions (VDD = 3.3V 0.15V, Ta = 0 to 70C) Conditions VIH = 2.4V VIL = 0.4V 1V/ns 2.0/0.8V K/K cross; C/C cross 0.8V 1V/ns 1.4V Fig. 1 -6- 1 Including scope and jig capacitance. 2 For tLZ, tHZ. Fig. 1.
I/O 50 50 1.4V I/O 5pF1 1178
Output Load (1)
Output Load (2) 2
3.3V
868
CXK77B3610GB
Register-Register mode Timing waveform of READ CYCLE
K
K tKP tS A0 to 14 n tH n+1
tKH tKL
n+2
W tS tH tS S tKQ tKQ G tLZ DQ0 to 35 Qn - 2 tOHZ tOLZ tHZ Qn - 1 Qn tOE tH
Timing waveform of WRITE CYCLE
K
K tS A0 to 14 n tH n+1 n+2
S
W/BWx
G
DQ0 to 35
Dn - 1
Dn
Dn + 1
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CXK77B3610GB
Register-Register mode Timing waveform of READ-WRITE-READ CYCLE I (S controlled)
K
K
A0 to 14
N
N+2
N+3
N+4
N+5
S
W/BWx
G = VIL DQ0 to 35 Qn - 1 Qn Dn + 2 Qn + 3
Reed N
Deselect (Hi-Z)
Write N + 2
Reed N + 3
Timing waveform of READ-WRITE-READ CYCLE II (G controlled)
K K
A0 to 14
N
N+2
N+3
N+4
N+5
S = VIL W/BWx
G
DQ0 to 35
Qn - 1
Qn
Dn + 2
Qn + 3
Reed N
Hi-Z; Write N + 2
Reed N + 3
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CXK77B3610GB
Register-Latch mode Timing waveform of READ CYCLE
K
K
tKP tS tH n+1
tKH tKL
A0 to 14
n
n+2
W tS tH tS S tKQ2 tKQ1 tKQ2 tOE tH tS tH
tKQ1 tAA G
tLZ2
tOHZ
tOLZ
tHZ
DQ0 to 35
Qn - 1
Qn
Qn + 1
Timing waveform of WRITE CYCLE
K
tKP
K tS A0 to 14 n
tH n+1 n+2
S
W/BWx
G
DQ0 to 35
Dn - 1
Dn
Dn + 1
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CXK77B3610GB
Register-Latch mode Timing waveform of READ-WRITE-READ CYCLE
K
K
tKP
tKP
tKP
tKP
A0 to 14
N tS tH tS
N+1
N+2
N+3
N+4
N+5
S
tH tKQ1
tS tKQ2
tH
W/BWx
tKQ2 tAA tKQ1 tWHZ tS tH tKQ2
G = VIL tLZ2 DQ0 to 35 Qn tKQ3 Reed N Write N + 1 Reed N + 2 Deselect (Hi-Z) Dn + 1 Qn + 2 tLZ1 Reed N + 4 Qn + 4
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CXK77B3610GB
Register-Flow Thru mode Timing waveform of READ CYCLE
K
K
tKP tS tH n+1
tKH tKL
A0 to 14
n
n+2
W tS tH tS S tKQ1 tKQ1 tAA G tOLZ tHZ tOE tH tS tH
tLZ1 DQ0 to 35 Qn - 1
tOHZ
Qn
Qn + 1
Timing waveform of WRITE CYCLE
K
K tS A0 to 14 n
tH n+1 n+2
S
W/BWx
G
DQ0 to 35
Dn - 1
Dn
Dn + 1
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CXK77B3610GB
Register-Flow Thru mode Timing waveform of READ-WRITE-READ CYCLE
K
K
A0 to 14 tS
N tH tS
N+1
N+2
N+3
N+4
N+5
S
tH tKQ1
tS
tH
W/BWx tAA tKO1 G = VIL DQ0 to 35 Qn tKQ3 Reed N Write N + 1 Reed N + 2 Deselect (Hi-Z) Dn + 1 Qn + 2 tLZ1 Reed N + 4 Qn + 4 tWHZ tS tH tKQ1
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CXK77B3610GB
Test Mode Description Fuctional Description The CXK77B3610 provides JTAG boundary scan interface using IEEE std. 1149.1 protocol. The test mode is intended to provided a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs other components and print circuit board. In conformance with IEEE std. 1149.1, the CXK77B3610 contains a TAP controller, Instruction register, Boundary scan register and Bypass register. Test Access Port (TAP) 4 pins as defined in Pin Description table are used to perform JTAG functions. TDI input pin is used to scan test data serially into one of three registers (Instruction register, Boundary scan register and Bypass register). TDO is output pin used to scan test data serially out. The TDI send the data into LSB of selected register and the MSB of the selected register feeds the data to TDO. TMS input pin controls the state transition of 16 state TAP controller as specified in IEEE std. 1149.1. Inputs on TDI, TMS are registered on the rising edge of TCK clock and the output data on TDO is presented on the falling edge of TCK. TDO driver is in active state only when TAP conroller is in Shift-IR state or in Shift-DR state. TAP Controller 16 state controller is implemented as specified in IEEE std. 1149.1. The controller enter reset state in one of three ways: 1. Power up 2. Apply logic 1 on TMS input pin on 5 consecutive TCK rising edges. Instruction Resister (3 bits) The JTAG Instruction resister is consisted of shift resister stage and parallel output latch. The register is 3 bits wide and is encoded as follow: Octal 0 1 2 3 4 5 6 7 MSB 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1 Bypass IDCODE. read device ID Sample-Z. Sample Inputs and tri-state DQs Bypass Sample. Sample Inputs. Private. Manufacturer use only. Bypass Bypass Instruction
Bypass Register (1 bit) The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides the minimum length serial path between TDI and TDO.
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CXK77B3610GB
ID Registers (32 bits) The ID Register are 32 bits wide and are listed as follow: ID [0] Sony ID Part Number Revision Number ID [11:1] ID [27:12] ID [31:28] 1 0000 1110 001 0000 0000 0000 0000 xxxx1
1 Please contact Sony Sales Department.
Boundary Scan Register (70 bits) The Boundary Scan Registers are 70 bits wide and are listed as follow: DQ A W, BWx S, G K, K, C, C ZZ Mode Place Holder 36 15 5 2 4 1 2 5
K/K, C/C inputs are sampled through one differential stage and internal inverted to generate internal K/K, C/C signals for scan registers. Place Holder are required for some NC pins to maintain 70 bits Scan Register for different types of same family SRAM and for density upgrade. All Place Holder Registers are connected to VSS internally regardless of pin connection externally.
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CXK77B3610GB
Scan Order (Order by exit sequence) 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 -- -- 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G -- 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R VSS VSS A A A A DQc DQc DQc DQc DQc DQc DQc DQc DQc /Wc VSS /S /C C /W /Wd DQd DQd DQd DQd DQd DQd DQd DQd DQd A A A M1 VSS VSS A A A A DQb DQb DQb DQb DQb DQb DQb DQb DQb /Wb /G K /K /Wa DQa DQa DQa DQa DQa DQa DQa DQa DQa ZZ A A A A M2 -- -- 5A 5C 6C 6A 6D 7D 6E 7E 6F 6G 7G 6H 7H 5G 4F 4K 4L 5L 7K 6K 7L 6L 6M 7N 6N 7P 6P 7T 5T 6R 4T 4P 5R 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
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CXK77B3610GB
Package Outline
Unit: mm
119 TERMINAL BGA (PLASTIC)
14.0 11.5 B
A
0.6 0.1 X C 3.19
U T R P N M L K J H G F E D C B A
7.62 1.27
0.84 19.5
1. 0
C
x4 0.10
1234567
3-
0.6 0.1 1.5
0.75 0.15
0.3 0.1
20.32
C AB
EPOXY RESIN COPPER-CLAD LAMINATE SOLDER 0.8g
22.0
0.35
1.27
C
SONY CODE EIAJ CODE JEDEC CODE
46 0. C
DETAIL X
BGA-119P-01
C 5 1.
0.15
C
PACKAGE STRUCTURE
PACKAGE MATERIAL BOARD MATERIAL TERMINAL MATERIAL PACKAGE WEIGHT
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